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Material Type: Artigo
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Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth ControlAbu-Rahma, M.H. ; Anis, M. ; Sei Seung YoonIEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.356-364 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space ApplicationsAgnesina, Anthony ; Yamaguchi, James ; Krutzik, Christian ; Carson, John ; Yang-Scharlotta, Jean ; Lim, Sung KyuIEEE transactions on very large scale integration (VLSI) systems, 2020-09, Vol.28 (9), p.2055-2068 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Cross-Layer Approximate Hardware Synthesis for Runtime Configurable AccuracyAlan, Tanfer ; Gerstlauer, Andreas ; Henkel, JorgIEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1231-1243 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design StrategiesAlioto, M ; Consoli, E ; Palumbo, GIEEE transactions on very large scale integration (VLSI) systems, 2011-05, Vol.19 (5), p.725-736 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number SystemsAmanollahi, Saba ; Jaberipur, GhassemIEEE transactions on very large scale integration (VLSI) systems, 2017-03, Vol.25 (3), p.954-961 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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EGRA: A Coarse Grained Reconfigurable Architectural TemplateAnsaloni, Giovanni ; Bonzini, Paolo ; Pozzi, LauraIEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1062-1074 [Periódico revisado por pares]New York, NY: IEEETexto completo disponível |
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Material Type: Artigo
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Behavioral simulation for analog system design verificationAntao, B.A.A. ; Brodersen, A.J.IEEE transactions on very large scale integration (VLSI) systems, 1995-09, Vol.3 (3), p.417-429 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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ARCHGEN: Automated synthesis of analog systemsAntao, B.A.A. ; Brodersen, A.J.IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.231-244 [Periódico revisado por pares]IEEETexto completo disponível |
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Material Type: Artigo
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An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine TransformAranda, Luis Alberto ; Sanchez-Macian, Alfonso ; Maestro, Juan AntonioIEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1336-1340 [Periódico revisado por pares]New York: IEEETexto completo disponível |
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Material Type: Artigo
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Enhancing Model Order Reduction for Nonlinear Analog Circuit SimulationAridhi, Henda ; Zaki, Mohamed H. ; Tahar, SofieneIEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.1036-1049 [Periódico revisado por pares]New York: IEEETexto completo disponível |