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Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs
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Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs

Min Xu ; Kurdahi, F.J.

IEEE transactions on very large scale integration (VLSI) systems, 1999-12, Vol.7 (4), p.411-418 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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2
ADC-Based Backplane Receiver Design-Space Exploration
ADC-Based Backplane Receiver Design-Space Exploration
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ADC-Based Backplane Receiver Design-Space Exploration

Chung, Hayun ; Wei, Gu-Yeon

IEEE transactions on very large scale integration (VLSI) systems, 2014-07, Vol.22 (7), p.1539-1547 [Periódico revisado por pares]

New York: IEEE

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3
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform
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An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform

Aranda, Luis Alberto ; Sanchez-Macian, Alfonso ; Maestro, Juan Antonio

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1336-1340 [Periódico revisado por pares]

New York: IEEE

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4
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
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An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop

Namgoong, Won

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.1025-1035 [Periódico revisado por pares]

New York: IEEE

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5
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design Strategies
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design Strategies
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Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design Strategies

Alioto, M ; Consoli, E ; Palumbo, G

IEEE transactions on very large scale integration (VLSI) systems, 2011-05, Vol.19 (5), p.725-736 [Periódico revisado por pares]

New York, NY: IEEE

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6
Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective
Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective
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Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective

Khan, Z. ; Arslan, T. ; Thompson, J.S. ; Erdogan, A.T.

IEEE transactions on very large scale integration (VLSI) systems, 2006-11, Vol.14 (11), p.1281-1286 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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7
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization
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Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization

Fan, Xin ; Zhang, Shutao ; Gemmeke, Tobias

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2495-2508 [Periódico revisado por pares]

New York: IEEE

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8
ARCHGEN: Automated synthesis of analog systems
ARCHGEN: Automated synthesis of analog systems
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ARCHGEN: Automated synthesis of analog systems

Antao, B.A.A. ; Brodersen, A.J.

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.231-244 [Periódico revisado por pares]

IEEE

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9
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
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Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design

Pereira, Pedro Taua Lopes ; Paim, Guilherme ; Costa, Patricia Ucker Leleu da ; Costa, Eduardo Antonio Cesar da ; de Almeida, Sergio Jose Melo ; Bampi, Sergio

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1402-1415 [Periódico revisado por pares]

New York: IEEE

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10
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
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Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Kim, Jinwoo ; Murali, Gauthaman ; Park, Heechun ; Qin, Eric ; Kwon, Hyoukjun ; Chekuri, Venkata Chaitanya Krishna ; Rahman, Nael Mizanur ; Dasari, Nihar ; Singh, Arvind ; Lee, Minah ; Torun, Hakki Mert ; Roy, Kallol ; Swaminathan, Madhavan ; Mukhopadhyay, Saibal ; Krishna, Tushar ; Lim, Sung Kyu

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2424-2437 [Periódico revisado por pares]

New York: IEEE

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