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1
Design Structure Matrix Extensions and Innovations: A Survey and New Opportunities
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Design Structure Matrix Extensions and Innovations: A Survey and New Opportunities

Browning, Tyson R.

IEEE transactions on engineering management, 2016-02, Vol.63 (1), p.27-52 [Peer Reviewed Journal]

New York: IEEE

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2
Digital Twin in the IoT Context: A Survey on Technical Features, Scenarios, and Architectural Models
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Digital Twin in the IoT Context: A Survey on Technical Features, Scenarios, and Architectural Models

Minerva, Roberto ; Lee, Gyu Myoung ; Crespi, Noel

Proceedings of the IEEE, 2020-10, Vol.108 (10), p.1785-1824 [Peer Reviewed Journal]

New York: IEEE

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3
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
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High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Ueno, Rei ; Homma, Naofumi ; Morioka, Sumio ; Miura, Noriyuki ; Matsuda, Kohei ; Nagata, Makoto ; Bhasin, Shivam ; Mathieu, Yves ; Graba, Tarik ; Danger, Jean-Luc

IEEE transactions on computers, 2020-04, Vol.69 (4), p.534-548 [Peer Reviewed Journal]

New York: IEEE

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4
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei ; Cao, Yu ; Vrudhula, Sarma ; Seo, Jae-sun

IEEE transactions on very large scale integration (VLSI) systems, 2018-07, Vol.26 (7), p.1354-1367 [Peer Reviewed Journal]

New York: IEEE

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5
On the features and challenges of security and privacy in distributed internet of things
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On the features and challenges of security and privacy in distributed internet of things

Roman, Rodrigo ; Zhou, Jianying ; Lopez, Javier

Computer networks (Amsterdam, Netherlands : 1999), 2013-07, Vol.57 (10), p.2266-2279 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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6
Constant Envelope Hybrid Precoding for Directional Millimeter-Wave Communications
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Constant Envelope Hybrid Precoding for Directional Millimeter-Wave Communications

Huang, Yongming ; Zhang, Jianjun ; Xiao, Ming

IEEE journal on selected areas in communications, 2018-04, Vol.36 (4), p.845-859 [Peer Reviewed Journal]

New York: IEEE

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7
On-Chip Interconnection Architecture of the Tile Processor
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On-Chip Interconnection Architecture of the Tile Processor

Wentzlaff, D. ; Griffin, P. ; Hoffmann, H. ; Liewei Bao ; Edwards, B. ; Ramey, C. ; Mattina, M. ; Chyi-Chang Miao ; Brown, J.F. ; Agarwal, A.

IEEE MICRO, 2007-09, Vol.27 (5), p.15-31 [Peer Reviewed Journal]

Los Alamitos: IEEE

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8
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
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TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Akopyan, Filipp ; Sawada, Jun ; Cassidy, Andrew ; Alvarez-Icaza, Rodrigo ; Arthur, John ; Merolla, Paul ; Imam, Nabil ; Nakamura, Yutaka ; Datta, Pallab ; Gi-Joon Nam ; Taba, Brian ; Beakes, Michael ; Brezzo, Bernard ; Kuang, Jente B. ; Manohar, Rajit ; Risk, William P. ; Jackson, Bryan ; Modha, Dharmendra S.

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-10, Vol.34 (10), p.1537-1557 [Peer Reviewed Journal]

New York: IEEE

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9
Data Center Network Virtualization: A Survey
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Data Center Network Virtualization: A Survey

Bari, M. F. ; Boutaba, R. ; Esteves, R. ; Granville, L. Z. ; Podlesny, M. ; Rabbani, M. G. ; Qi Zhang ; Zhani, M. F.

IEEE Communications surveys and tutorials, 2013, Vol.15 (2), p.909-928 [Peer Reviewed Journal]

IEEE

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10
Biophilic design in architecture and its contributions to health, well-being, and sustainability: A critical review
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Biophilic design in architecture and its contributions to health, well-being, and sustainability: A critical review

Zhong, Weijie ; Schröder, Torsten ; Bekkering, Juliette

Frontiers of architectural research, 2022-02, Vol.11 (1), p.114-141 [Peer Reviewed Journal]

Elsevier B.V

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