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3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
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3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

Bhoj, Ajay N. ; Joshi, Rajiv V. ; Jha, Niraj K.

IEEE transactions on very large scale integration (VLSI) systems, 2013-11, Vol.21 (11), p.2094-2105 [Periódico revisado por pares]

New York, NY: IEEE

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2
692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS
692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS
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692-nW Advanced Encryption Standard (AES) on a 0.13-μm CMOS

GOOD, Tim ; BENAISSA, Mohammed

IEEE transactions on very large scale integration (VLSI) systems, 2010-12, Vol.18 (12), p.1753-1757 [Periódico revisado por pares]

New York, NY: Institute of Electrical and Electronics Engineers

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3
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
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81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC

KIM, Donghyun ; KIM, Kwanho ; KIM, Joo-Young ; LEE, Seungjin ; LEE, Se-Joong ; YOO, Hoi-Jun

IEEE transactions on very large scale integration (VLSI) systems, 2009-03, Vol.17 (3), p.370-383 [Periódico revisado por pares]

New York, NY: IEEE

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4
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
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A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

Chung, Ching-Che ; Su, Wei-Siang ; Lo, Chi-Kuang

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.408-412 [Periódico revisado por pares]

New York: IEEE

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5
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
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A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency

TSAI, Kun-Hung ; LIU, Shen-Iuan

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.80-88 [Periódico revisado por pares]

New York, NY: IEEE

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6
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL
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A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL

Chou, Ming-Han ; Liu, Shen-Iuan

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2474-2478 [Periódico revisado por pares]

New York: IEEE

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7
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
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A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging

Chen, Poki ; Hsiao, Ya-Yun ; Chung, Yi-Su ; Tsai, Wei Xiang ; Lin, Jhih-Min

IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.114-124 [Periódico revisado por pares]

New York: IEEE

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8
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
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A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices

Garrido, Mario ; Sanchez, Miguel Angel ; Lopez-Vallejo, Maria Luisa ; Grajal, Jesus

IEEE transactions on very large scale integration (VLSI) systems, 2017-01, Vol.25 (1), p.375-379 [Periódico revisado por pares]

New York: IEEE

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9
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
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A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory

Ho, Kin-Chu ; Chen, Chih-Lung ; Chang, Hsie-Chia

IEEE transactions on very large scale integration (VLSI) systems, 2016-04, Vol.24 (4), p.1293-1304 [Periódico revisado por pares]

New York: IEEE

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10
A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS
A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS
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A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS

Masoumi Farahabadi, Payam ; Moez, Kambiz

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1909-1916 [Periódico revisado por pares]

New York: IEEE

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