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0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell
0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell
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0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell

SHAIK, Khaja Ahmad ; ITOH, Kiyoo ; AMARA, Amara

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2016/02/01, Vol.E99.A(2), pp.523-530 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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2
1.0 Gbps CMOS oversampling data recovery circuit with fine delay generation method
1.0 Gbps CMOS oversampling data recovery circuit with fine delay generation method
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1.0 Gbps CMOS oversampling data recovery circuit with fine delay generation method

Park, Jun-Young ; Kang, Jin-Ku

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2000-06, Vol.E83-A (6), p.1100-1105 [Periódico revisado por pares]

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3
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters
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1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

UENO, T. ; ITO, T. ; KUROSE, D. ; YAMAJI, T. ; ITAKURA, T.

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2008-02, Vol.E91-A (2), p.454-460 [Periódico revisado por pares]

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4
1.5 GHz CMOS low noise amplifier
1.5 GHz CMOS low noise amplifier
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1.5 GHz CMOS low noise amplifier

Fujimoto, Ryuichi ; Otaka, Shoji ; Iwai, Hiroshi ; Tanimoto, Hiroshi

IEICE transactions on fundamentals of electronics, communications and computer sciences, 1998-03, Vol.E81-A (3), p.382-388 [Periódico revisado por pares]

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5
1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application
1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application
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1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application

KAWAMOTO, Takashi ; SUZUKI, Masato ; NOTO, Takayuki

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2015, Vol.E98.A(2), pp.485-491 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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6
A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS
A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS
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A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-µm CMOS

KURAMOCHI, Yasuhide ; MATSUZAWA, Akira ; KAWABATA, Masayuki

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2009/02/01, Vol.E92.A(2), pp.360-366 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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7
A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-.MU.m CMOS
A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-.MU.m CMOS
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A 0.027-mm2 Self-Calibrating Successive Approximation ADC Core in 0.18-.MU.m CMOS

KURAMOCHI, Yasuhide ; MATSUZAWA, Akira ; KAWABATA, Masayuki

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2009, Vol.E92-A (2), p.360-366 [Periódico revisado por pares]

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8
A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers
A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers
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A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers

ITO, Tomohiko ; ITAKURA, Tetsuro

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2010/02/01, Vol.E93.A(2), pp.395-401 [Periódico revisado por pares]

The Institute of Electronics, Information and Communication Engineers

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9
A 1-V 2-GHz RF receiver with 49 dB of image rejection in CMOS/SIMOX
A 1-V 2-GHz RF receiver with 49 dB of image rejection in CMOS/SIMOX
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A 1-V 2-GHz RF receiver with 49 dB of image rejection in CMOS/SIMOX

Ugajin, Mamoru ; Kodate, Junichi ; Tsukahara, Tsuneo

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2002-02, Vol.E85-A (2), p.293-299 [Periódico revisado por pares]

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10
A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC
A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC
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A 10-bit 800-Column Low-Power RAM Bank Including Energy-Efficient D-Flip-Flops for a Column-Parallel ADC

OKURA, S. ; OKURA, T. ; INDIKA U.K., B. A. ; TANIGUCHI, K.

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2007-02, Vol.E90-A (2), p.358-364 [Periódico revisado por pares]

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