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A scheme for multiple on-chip signature checking for embedded SRAMS
A scheme for multiple on-chip signature checking for embedded SRAMS
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A scheme for multiple on-chip signature checking for embedded SRAMS

Abdulla, M.F. ; Ravikumar, C.P. ; Kumar, Anshul

Journal of systems architecture, 2000-01, Vol.46 (2), p.181-199 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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2
Recursive design of hardware priority queues
Recursive design of hardware priority queues
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Recursive design of hardware priority queues

Afek, Y. ; Bremler-Barr, A. ; Schiff, L.

Computer networks (Amsterdam, Netherlands : 1999), 2014-06, Vol.66, p.52-67 [Peer Reviewed Journal]

Kidlington: Elsevier B.V

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3
High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media
High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media
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High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media

Ahmad, Balal ; Ahmadinia, Ali ; Arslan, Tughrul

Journal of systems architecture, 2010-11, Vol.56 (11), p.597-615 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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4
Electronic nose system on the Zynq SoC platform
Electronic nose system on the Zynq SoC platform
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Electronic nose system on the Zynq SoC platform

Ait Si Ali, Amine ; Djelouat, Hamza ; Amira, Abbes ; Bensaali, Faycal ; Benammar, Mohieddine ; Bermak, Amine

Microprocessors and microsystems, 2017-08, Vol.53, p.145-156 [Peer Reviewed Journal]

Kidlington: Elsevier B.V

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5
Sign detection in residue arithmetic units
Sign detection in residue arithmetic units
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Sign detection in residue arithmetic units

Alia, Giuseppe ; Martinelli, Enrico

Journal of systems architecture, 1998-11, Vol.45 (3), p.251-258 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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6
Discriminatory processor sharing queues with stationary ergodic service times and the performance of TCP in overload
Discriminatory processor sharing queues with stationary ergodic service times and the performance of TCP in overload
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Discriminatory processor sharing queues with stationary ergodic service times and the performance of TCP in overload

Altman, Eitan ; Jiménez, Tania ; Kofman, Daniel

Computer networks (Amsterdam, Netherlands : 1999), 2010-06, Vol.54 (9), p.1509-1519 [Peer Reviewed Journal]

Kidlington: Elsevier B.V

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7
A multilevel partitioning approach for efficient tasks allocation in heterogeneous distributed systems
A multilevel partitioning approach for efficient tasks allocation in heterogeneous distributed systems
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A multilevel partitioning approach for efficient tasks allocation in heterogeneous distributed systems

Arafeh, Bassel ; Day, Khalid ; Touzene, Abderezak

Journal of systems architecture, 2008-05, Vol.54 (5), p.530-548 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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8
Network processor requirements and benchmarking
Network processor requirements and benchmarking
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Network processor requirements and benchmarking

Arts, F. ; Barri, P. ; Clemminck, I. ; Niemegeers, A. ; Pauwels, B. ; Taildeman, G. ; Vrana, M.

Computer networks (Amsterdam, Netherlands : 1999), 2003-04, Vol.41 (5), p.549-562 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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9
Efficient dual-precision floating-point fused-multiply-add architecture
Efficient dual-precision floating-point fused-multiply-add architecture
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Efficient dual-precision floating-point fused-multiply-add architecture

Arunachalam, V. ; Joseph Raj, Alex Noel ; Hampannavar, Naveen ; Bidul, C.B.

Microprocessors and microsystems, 2018-03, Vol.57, p.23-31 [Peer Reviewed Journal]

Kidlington: Elsevier B.V

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10
Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level
Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level
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Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level

Asaduzzaman, Abu ; Sibai, Fadi N. ; Rani, Manira

Journal of systems architecture, 2010-04, Vol.56 (4), p.151-162 [Peer Reviewed Journal]

Amsterdam: Elsevier B.V

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