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Refinado por: Nome da Publicação: Ieee Transactions On Very Large Scale Integration remover assunto: Technology remover Software remover
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Exact moment matching model of transmission lines and application to interconnect delay estimation
Exact moment matching model of transmission lines and application to interconnect delay estimation
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Exact moment matching model of transmission lines and application to interconnect delay estimation

Qingjian Yu ; Kuh, E.S.

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.311-322 [Periódico revisado por pares]

IEEE

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2
Predictive system shutdown and other architectural techniques for energy efficient programmable computation
Predictive system shutdown and other architectural techniques for energy efficient programmable computation
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Predictive system shutdown and other architectural techniques for energy efficient programmable computation

Srivastava, M.B. ; Chandrakasan, A.P. ; Brodersen, R.W.

IEEE transactions on very large scale integration (VLSI) systems, 1996-03, Vol.4 (1), p.42-55 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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3
VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept
VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept
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VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept

Eklund, J.-E. ; Svensson, C. ; Astrom, A.

IEEE transactions on very large scale integration (VLSI) systems, 1996-09, Vol.4 (3), p.322-335 [Periódico revisado por pares]

IEEE

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4
Protocol selection and interface generation for HW-SW codesign
Protocol selection and interface generation for HW-SW codesign
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Protocol selection and interface generation for HW-SW codesign

Daveau, J.-M. ; Marchioro, G.F. ; Ben-Ismail, T. ; Jerraya, A.A.

IEEE transactions on very large scale integration (VLSI) systems, 1997-03, Vol.5 (1), p.136-144 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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5
A solution methodology for exact design space exploration in a three-dimensional design space
A solution methodology for exact design space exploration in a three-dimensional design space
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A solution methodology for exact design space exploration in a three-dimensional design space

Chaudhuri, S. ; Blthye, S.A. ; Walker, R.A.

IEEE transactions on very large scale integration (VLSI) systems, 1997-03, Vol.5 (1), p.69-81 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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6
Power analysis and minimization techniques for embedded DSP software
Power analysis and minimization techniques for embedded DSP software
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Power analysis and minimization techniques for embedded DSP software

Mike Tien-Chien Lee ; Tiwari, V. ; Malik, S. ; Fujita, M.

IEEE transactions on very large scale integration (VLSI) systems, 1997-03, Vol.5 (1), p.123-135 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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7
Electro-thermal and logi-thermal simulation of VLSI designs
Electro-thermal and logi-thermal simulation of VLSI designs
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Electro-thermal and logi-thermal simulation of VLSI designs

Szekely, V. ; Poppe, A. ; Pahi, A. ; Csendes, A. ; Hajas, G. ; Rencz, M.

IEEE transactions on very large scale integration (VLSI) systems, 1997-09, Vol.5 (3), p.258-269 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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8
Electro-thermal circuit simulation using simulator coupling
Electro-thermal circuit simulation using simulator coupling
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Electro-thermal circuit simulation using simulator coupling

Wunsche, S. ; Clauss, C. ; Schwarz, P. ; Winkler, F.

IEEE transactions on very large scale integration (VLSI) systems, 1997-09, Vol.5 (3), p.277-282 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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9
Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications
Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications
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Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications

Jun Ma ; Han-Bin Liang ; Pryor, R.A. ; Cheng, S. ; Kaneshiro, M.H. ; Kyono, C.S. ; Papworth, K.

IEEE transactions on very large scale integration (VLSI) systems, 1997-12, Vol.5 (4), p.352-359 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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10
Intrinsic MOSFET parameter fluctuations due to random dopant placement
Intrinsic MOSFET parameter fluctuations due to random dopant placement
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Intrinsic MOSFET parameter fluctuations due to random dopant placement

Xinghai Tang ; De, V.K. ; Meindl, J.D.

IEEE transactions on very large scale integration (VLSI) systems, 1997-12, Vol.5 (4), p.369-376 [Periódico revisado por pares]

Piscataway, NJ: IEEE

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