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Verifying Parallel Code After Refactoring Using Equivalence Checking
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Verifying Parallel Code After Refactoring Using Equivalence Checking

Abadi, Moria ; Keidar-Barner, Sharon ; Pidan, Dmitry ; Veksler, Tatyana

International journal of parallel programming, 2019-02, Vol.47 (1), p.59-73 [Periódico revisado por pares]

New York: Springer US

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2
High-level modeling and FPGA prototyping of produced order parallel queue processor core
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High-level modeling and FPGA prototyping of produced order parallel queue processor core

ABDERAZEK, Ben A ; YOSHINAGA, Tsutomu ; SOWA, Masahiro

The Journal of supercomputing, 2006-10, Vol.38 (1), p.3-15 [Periódico revisado por pares]

Heidelberg: Springer

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3
Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture
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Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture

Abderazek, Ben Abdallah ; Masuda, Masashi ; Canedo, Arquimedes ; Kuroda, Kenichi

The Journal of supercomputing, 2011-09, Vol.57 (3), p.314-338 [Periódico revisado por pares]

Boston: Springer US

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4
Development of the omnidirectional transporting table based on omnidirectional driving gear
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Development of the omnidirectional transporting table based on omnidirectional driving gear

Abe, Kazuki ; Matsui, Gaku ; Tadakuma, Kenjiro ; Yamano, Mitsuhiro ; Tadakuma, Riichiro

Advanced robotics, 2020-03, Vol.34 (6), p.358-374 [Periódico revisado por pares]

Taylor & Francis

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5
Study on hypercompact and lightweight data logger separators for wild animals
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Study on hypercompact and lightweight data logger separators for wild animals

Abe, Takuma ; Kubo, Natsumi ; Abe, Kazuki ; Suzuki, Hirokazu ; Yoda, Ken ; Tadakuma, Riichiro ; Tsumaki, Yuichi

Advanced robotics, 2021-01, Vol.35 (2), p.81-92 [Periódico revisado por pares]

Taylor & Francis

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6
Five-Card AND Computations in Committed Format Using Only Uniform Cyclic Shuffles
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Five-Card AND Computations in Committed Format Using Only Uniform Cyclic Shuffles

Abe, Yuta ; Hayashi, Yu-ichi ; Mizuki, Takaaki ; Sone, Hideaki

New generation computing, 2021-04, Vol.39 (1), p.97-114 [Periódico revisado por pares]

Tokyo: Ohmsha

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7
Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats
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Artigo
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Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats

Abellán, José L. ; Fernández, Juan ; Acacio, Manuel E.

The Journal of supercomputing, 2010-08, Vol.53 (2), p.247-268 [Periódico revisado por pares]

Boston: Springer US

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8
Delay time compensation based on coefficient of restitution for collision hybrid motion simulator
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Delay time compensation based on coefficient of restitution for collision hybrid motion simulator

Abiko, Satoko ; Satake, Yoshikazu ; Jiang, Xin ; Tsujita, Teppei ; Uchiyama, Masaru

Advanced robotics, 2014-09, Vol.28 (17), p.1177-1188 [Periódico revisado por pares]

Taylor & Francis

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9
Supercomputing applications to the numerical modeling of industrial and applied mathematics problems
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Supercomputing applications to the numerical modeling of industrial and applied mathematics problems

ACEBRON, Juan A ; SPIGLER, Renato

The Journal of supercomputing, 2007-04, Vol.40 (1), p.67-80 [Periódico revisado por pares]

Heidelberg: Springer

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10
Extraction and evolution of architectural variability models in plugin-based systems
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Extraction and evolution of architectural variability models in plugin-based systems

Acher, Mathieu ; Cleve, Anthony ; Collet, Philippe ; Merle, Philippe ; Duchien, Laurence ; Lahire, Philippe

Software and systems modeling, 2014-10, Vol.13 (4), p.1367-1394 [Periódico revisado por pares]

Berlin/Heidelberg: Springer Berlin Heidelberg

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