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An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study
An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study
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An FPGA-Based Hardware Accelerator for CNNs Inference on Board Satellites: Benchmarking with Myriad 2-Based Solution for the CloudScout Case Study

Rapuano, Emilio ; Meoni, Gabriele ; Pacini, Tommaso ; Dinelli, Gianmarco ; Furano, Gianluca ; Giuffrida, Gianluca ; Fanucci, Luca

Remote sensing (Basel, Switzerland), 2021-04, Vol.13 (8), p.1518 [Periódico revisado por pares]

Basel: MDPI AG

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2
An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick
An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick
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An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

Dinelli, Gianmarco ; Meoni, Gabriele ; Rapuano, Emilio ; Benelli, Gionata ; Fanucci, Luca Margala, Martin ; Martin Margala

International journal of reconfigurable computing, 2019-10, Vol.2019, p.1-13 [Periódico revisado por pares]

New York: Hindawi

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3
A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard
A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard
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A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard

Dello Sterpaio, Luca ; Marino, Antonino ; Nannipieri, Pietro ; Dinelli, Gianmarco ; Davalle, Daniele ; Fanucci, Luca

Sensors (Basel, Switzerland), 2019-11, Vol.19 (22), p.5013 [Periódico revisado por pares]

Switzerland: MDPI AG

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4
A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case
A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case
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A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case

NANNIPIERI, Pietro ; DINELLI, Gianmarco ; FANUCCI, Luca

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2019/05/01, Vol.E102.A(5), pp.747-749 [Periódico revisado por pares]

Tokyo: The Institute of Electronics, Information and Communication Engineers

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5
Design of a Reduced SpaceFibre Interface: An Enabling Technology for Low-Cost Spacecraft High-Speed Data-Handling
Design of a Reduced SpaceFibre Interface: An Enabling Technology for Low-Cost Spacecraft High-Speed Data-Handling
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Design of a Reduced SpaceFibre Interface: An Enabling Technology for Low-Cost Spacecraft High-Speed Data-Handling

Dinelli, Gianmarco ; Nannipieri, Pietro ; Davalle, Daniele ; Fanucci, Luca

Aerospace, 2019-09, Vol.6 (9), p.101 [Periódico revisado por pares]

Basel: MDPI AG

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6
MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs
MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs
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MEM-OPT: A Scheduling and Data Re-Use System to Optimize On-Chip Memory Usage for CNNs On-Board FPGAs

Dinelli, Gianmarco ; Meoni, Gabriele ; Rapuano, Emilio ; Pacini, Tommaso ; Fanucci, Luca

IEEE journal on emerging and selected topics in circuits and systems, 2020-09, Vol.10 (3), p.335-347 [Periódico revisado por pares]

Piscataway: IEEE

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7
Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator
Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator
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Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator

Dinelli, Gianmarco ; Meoni, Gabriele ; Rapuano, Emilio ; Fanucci, Luca

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

IEEE

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8
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation
The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation
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The very high-speed SpaceFibre multi-lane CoDec: Implementation and experimental performance evaluation

Dinelli, Gianmarco ; Nannipieri, Pietro ; Marino, Antonino ; Fanucci, Luca ; Dello Sterpaio, Luca

Acta astronautica, 2021-02, Vol.179, p.462-470 [Periódico revisado por pares]

Elmsford: Elsevier Ltd

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9
A Multi-Cache System for On-Chip Memory Optimization in FPGA-Based CNN Accelerators
A Multi-Cache System for On-Chip Memory Optimization in FPGA-Based CNN Accelerators
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A Multi-Cache System for On-Chip Memory Optimization in FPGA-Based CNN Accelerators

Pacini, Tommaso ; Rapuano, Emilio ; Dinelli, Gianmarco ; Fanucci, Luca

Electronics (Basel), 2021-10, Vol.10 (20), p.2514 [Periódico revisado por pares]

Basel: MDPI AG

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10
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface
A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface
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A serial high-speed satellite communication CODEC: Design and implementation of a SpaceFibre interface

Nannipieri, Pietro ; Dinelli, Gianmarco ; Marino, Antonino ; Dello Sterpaio, Luca ; Leoni, Alessandro ; Fanucci, Luca ; Davalle, Daniele

Acta astronautica, 2020-04, Vol.169, p.206-215 [Periódico revisado por pares]

Elmsford: Elsevier Ltd

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